• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Methods for matching features in patterns for electronic designs involve inputting a set of pattern data for solid state or flat panel displays, the set of pattern data including a plurality of features. Each feature of the plurality of features is classified, the classifying being based on a geometric context defined by shapes in a region. Machine learning techniques are used in classification.
    公开号:AT524013A2
    申请号:T9073/2020
    申请日:2020-02-22
    公开日:2022-01-15
    发明作者:Niewczas Mariusz；Shendre Abhishek
    申请人:D2S Inc；
    IPC主号:
    专利说明:

    RELATED APPLICATIONS
    This application claims priority to US Nonprovisional Patent Application Serial No. 16/793,390, filed February 18, 2020, entitled "Methods and Systems for Classifying Features in Electronic Designs"; claiming priority from U.S. Provisional Patent Application No. 62/810,168, filed February 25, 2019, entitled "Methods and Systems for Classifying Features on Solid State or Flat Panel Display Shape Data"; which are hereby incorporated by reference in their entirety for all purposes.
    BACKGROUND
    [0002] The present disclosure relates to lithography, and more particularly to the design and fabrication of a surface, which may be a reticle, a wafer, or any other surface, using charged particle beam lithography.
    In lithography, the lithographic mask or reticle includes geometric patterns that correspond to circuit components to be integrated on a substrate. The patterns used to fabricate the reticle can be created using computer-aided design (CAD) software or programs. In designing the patterns, the CAD program can follow a set of predetermined design rules to create the reticle. These rules are set by processing, design, and end-use constraints. An example of an end-use limitation is defining the geometry of a transistor in a way that it cannot perform adequately at the required supply voltage. In particular, design rules can define the space tolerance between circuit devices or interconnect lines. For example, the design rules are used to ensure that the circuit devices or lines do not interact with each other in an undesired manner. For example, the design rules are used to
    prevent wires from getting so close that they short circuit
    2 can cause. The limitations of the design rules reflect, among other things, the smallest dimensions that can be reliably manufactured. When referring to these small dimensions, one usually introduces the concept of a critical dimension. These are defined, for example, as the important widths or areas of a feature, or the important space between two features, or important spatial areas, i.e. those dimensions that require precise control. Due to the nature of integrated circuit designs, many patterns are repeated at various locations in a design. A pattern can be repeated hundreds or thousands of times - each copy of the pattern is called an instance. When a design rule violation is found in such a pattern, hundreds or thousands of violations can be reported - one for each instance of the pattern.
    A goal in the manufacture of integrated circuits by optical lithography is to reproduce the original circuit design on a substrate using a reticle, where the reticle, sometimes referred to as a mask or photomask, is a surface lithographed with a Charged particle beam can be exposed. Integrated circuit manufacturers are always striving to use semiconductor wafer real estate as efficiently as possible. Engineers continue to shrink circuit sizes to make integrated circuits contain more circuit elements and consume less power. As the critical dimension of an integrated circuit is reduced and its circuit density increases, the critical dimension of the circuit pattern or physical design approaches the resolution limit of the optical exposure tool used in conventional optical lithography. As the critical dimensions of the circuit pattern shrink and approach the resolution level of the exposure tool, accurate transfer of the physical design to the actual circuit pattern developed on the resist layer becomes difficult. To promote the use of optical lithography to transfer patterns with features smaller than the wavelength of light used in the optical lithography process
    is used, a process was developed that is called optical
    3 optical proximity correction (OPC) is known. OPC modifies the physical design to compensate for distortions caused by effects such as optical diffraction and the optical interaction of features with neighboring features. Resolution enhancement technologies performed with a reticle include OPC and inverse lithography (ILT) technology.
    [0005] OPC can add sub-resolution lithographic features to mask patterns to reduce differences between the original physical design pattern, i.e. the design, and the final transferred circuit pattern on the substrate. The sub-resolution lithographic features interact with the original physical design patterns and with each other, compensating for proximity effects to enhance the final transferred circuit pattern. A feature added to improve pattern transfer is called "serifs". Serifs are small features that improve precision or resistance to manufacturing variations when printing a particular feature. An example of a serif is a small feature positioned at a corner of a pattern to sharpen the corner in the final rendered image. Patterns to be printed on the substrate are called key features. Serifs are part of a key feature. It is customary to discuss the OPC decorated patterns to be written on a reticle in terms of main features, i.e. features reflecting the design before OPC decoration, and OPC features, the OPC features being serifs, jogs, sub-resolution auxiliary features (sub-resolution assist features - SRAF) and negative features. OPC features are subject to various design rules, for example a rule based on the size of the smallest feature that can be transferred to the wafer using optical lithography. Other design rules may originate from the mask making process or, if a charged particle beam character projection writing system is used to form the pattern on a reticle, from the stencil making process.
    In optical lithography, the production of the desired
    pattern on the reticle or photomask is a critical step. Because the pattern
    4 is replicated on the photomask during the optical lithography process, there must be no defects on the photomask that result in a defect being printed onto the substrate during the optical lithography step. Therefore, newly manufactured photomasks are inspected to detect such potential defects. Potential defects are further analyzed to determine if the defect is genuine and needs to be repaired before the mask is used in production. SUMMARY
    Methods for matching features in patterns for electronic designs involve inputting a set of pattern data for solid state or flat panel displays, the set of pattern data including a plurality of features. Each feature of the plurality of features is classified, the classifying being based on a geometric context defined by shapes in a region. Machine learning techniques are used in classification.
    BRIEF DESCRIPTION OF THE DRAWINGS
    FIG. 1 is a representation of image data as a compressed encoding.
    FIG. 2A-2B show two mask/wafer artifact classifications according to some embodiments.
    [0010] FIG. 3 shows mean images computed from features in a cluster, according to some embodiments.
    [0011] FIG. 4A-4F show example average images used to measure clustering quality based on blurring, according to some embodiments.
    FIG. 5 shows features in a distance-ordered cluster, according to some embodiments.
    FIG. 6 is a schematic representation of a GPU system diagram according to some embodiments.
    FIG. 7 is a flowchart of methods for matching features in a pattern, according to some embodiments.
    [0015] FIG. 8 is a flowchart showing the method of matching features in a pattern using averagers for each
    classification according to some embodiments.
    DETAILED DESCRIPTION OF EMBODIMENTS
    In the design and manufacture of electronic designs such as integrated circuits and flat panel displays, there are several processes where comparison of the two-dimensional (2D) shape features in the design, the manufactured photomask, or the manufactured substrate is useful. Due to the very large number of features in today's designs, the speed of the comparison is important. Comparing compressed data can theoretically be faster than comparing uncompressed data because there is less data to compare. However, the time required to create the compressed representation must also be taken into account. Standard compression techniques are impractical because they take too long to compute. In U.S. Patent Application No. 16/793,152, entitled "Methods and Systems for Compressing Shape Data for Electronic Designs," incorporated herein by reference, data compression using neural network machine learning can produce a faster compression method, as described in FIG. 1 of the present application, once a mask image (input 100} has been compressed by an encoder 104 derived through machine learning based on a neural network, the compressed data 106 (referred to as "encoded image vector") can be used for classification In the present embodiments, unique classification techniques are described that enhance the analysis of compressed data.
    The two-dimensional data in designs for integrated circuits or flat panel displays is very limited in terms of the possible types of features compared to, for example, generalized line drawings. Similarly, the types of features that can be found in scanning electron microscope (SEM) photographs of manufactured photomasks or fabricated substrates are quite limited. Using machine learning techniques, these constraints allow for very high classification factors to be achieved.
    In some embodiments, autoencoding can be used for classification
    or categorization can be used. Since in the compressed data 106 in
    6 FIG. 1 more features are available, measuring the similarity between images is simplified by comparing all features. In some embodiments, the present methods remove undifferentiated data from the original input 100 (e.g., a 2D image or other representation of shapes) and find an encoding that has high information density (more features) such that the multi-dimensional categorization space is similar things close together and different things far apart without the total multidimensional volume of the whole space being too big. The present methods create a higher density of this total volume, making searching in this volume much more efficient. The training precomputes a network of relationships with "weights" based on the frequency of frequent occurrences. The classification is a very quick evaluation of this precomputed network to look for intersections that the encoder 104 applies to a given input.
    In conventional approaches, a geometric rules checker analyzes geometric data (e.g., mask design or wafer design or other two-dimensional geometric data) and reports errors such as "these shapes are too close together relative to the minimum space rule" or "this part of this shape is too small relative to the minimum size rule.” A term used to describe such errors is “Edge Placement Error” or EPE. When applied to the scale of a semiconductor (or flat panel display) mask - e.g. approximately 130mm x 100mm with a placement resolution of 0.1nm for a semiconductor mask - one of the practical problems is working through all reported errors to find out , which to look out for Other bugs reported include those detected by XOR, detection by other methods, or other types of bugs, All bugs are reported using a known set of rules,
    There are often thousands of errors "of the same kind" that violate the same rule. Once a problem triggers a bug, so many instances of similar situations create thousands of bugs that they mask other bugs that are different but important to note.
    For example, a single rule violation of a 1000-mail placed instance
    7725
    7 be more severe in certain areas. A classification of similar placements or geometric context in the present disclosure further distinguishes the 1000 errors,
    The present methods include classification modules that automatically classify reported errors based on the geometric context defined by shapes in a region. For example, a region can be a section of a mask design. In the present embodiments, assuming the image has a mask, wafer, or design shape, the process of encoding an image captures and encodes similarities between the possible shapes, allowing shapes to be compared and coded for a variety of applications classify. For example, if 2000 bugs are reported for a particular design, the current classification engines automatically group the bugs into "different types" and (possibly in an overlapping way: e.g. single vs. multiple tagging, where a bug may fall into multiple categories) . In single label classification, classes are exclusive, so each bug belongs to one class, while in multiple label classification, each bug can belong to more than one class. These classifications are categorizations of the similarity of shapes in a region, but do not identify specific types of bugs,
    The methods involve inputting a set of sample data for solid state or flat panel displays, the sample data including a plurality of features. Each feature of the plurality of features is classified into classifications using machine learning techniques. The classification can be based on a geometric context defined by shapes in a region. A feature in the set of sample data can be included in more than a single classification. The set of pattern data may include a set of suspect sites from the mask inspection and/or a set of reported defects from a geometric inspector. The methods may also include compressing the input pattern data, classifying the compressed
    Sample data are used.
    In some embodiments, the set of pattern data may include simulated mask data enhanced by OPC. A set of simulated contours generated from the simulated mask data is examined for EPE, resulting in a set of errors. Adding the OPC enhanced simulated mask data and the set of errors to the set of pattern data increases the variety of features to be classified.
    An important part of defect classification with machine learning is the automatic coding of the 2D contours of design, mask or wafer shapes. Such "categorization" has already been performed in electronic design automation. Typically, however, traditional categorization uses exact matches of rectilinear shapes from CAD designs. In contrast, machine learning error classification in the present embodiments can identify "similar" configurations of shapes or operate in a curved space by using simulated or actual physical images of fabricated surfaces in semiconductor wafers or masks or flat panel displays or their mask fabrication rooms. For example, FIG. 2A shows a set of images that have been categorized into a cluster in accordance with some embodiments, and FIG. 2B is a set of images classified in another cluster. As can be seen, the images within each cluster FIG. 2A or FIG. 2B have features that are similar to each other, but the classification module has recognized that the placement and types of features in the images in FIG. 2A differs from those in FIG. 2B distinguish. In some embodiments, an autoencoder is used in compression and/or classification. Encoded features from compression can be vectors.
    The output can be based on the input CAD shapes (which are usually rectilinear shapes, but can also be curved shapes) or post-OPC shapes that describe soft mask shapes that best produce the shapes on the wafer that the closest to desired CAD shapes, categorized or classified, post-OPC shapes are typically rectilinear, but embodiments may also (particularly
    with the output of next generation OPC software) curved shapes
    9 as made possible by writing multi-beam masks that do not have the rectangular boundaries of VSB-based mask writing. The output shapes could also represent simulated curved contours,
    When applying the methods of the present disclosure to SEM (Scanning Electron Microscope), images of physically fabricated masks or wafers can be used to automatically categorize identified defects. In semiconductor manufacturing, potential defects on masks are identified by mask inspection, which captures the image of the entire mask. This image is fuzzy and relatively low-resolution, but shows the entire mask. The image is intended to identify suspect areas that require further inspection. This further inspection is accomplished through much more accurate SEM images captured and analyzed with defect inspection SEM machines (as opposed to CD-REM machines which are designed to measure distances). SEM machines provide a very clear image in detail, but they can only pick up an order field from 1 µm x 1 µm to 10 µm x 10 µm. Thus, suspect areas are identified in the full-field mask image captured by inspection, then details of suspect areas are examined in the SEM. In the peak nodes, the number of identified suspect areas as well as the number of actual problems on a typical production mask is much larger than before. Ten years ago maybe tens of problems were fixed on masks, and masks with too many flaws were discarded and remade. Currently, among the top masks, hundreds of problems are common and fixed, Manufacturers no longer choose to remake defective masks because the probability is too high that the new one also has hundreds of (different) problems. The repair of defects is unique in mask manufacturing; Wafers are not repaired, masks are worth repairing because each wafer the mask produces has a specific defect on the mask.
    In the machine learning-based classification in the present embodiments, if an SEM photo of one or a few suspect locations shows that no actual problem - i.e. a defect -
    exists, the SEM imaging of other sites in question in the same category
    10 are avoided. This can significantly reduce the time required to inspect the mask.
    In some embodiments, the quality of a classification or a cluster of features (ie, a classification is a cluster of features) can be determined by generating a mean cluster image, as shown in FIG Clusters containing images 300, 302, 304, 306, 308, 310, 312, 314 and an average image 350 for clusters containing images 330, 332, 334, 336, 338, 340 are shown of visible visual blurring in mean cluster images 320 and 350 indicates the variation in the various features in the classification or cluster of features More blurring indicates greater variation, as shown in FIGs variation in Figures 4A and 4D is less than in Figures 45 and 4E, which is less than in Figures 4C and 4F In some embodiments, a Gaussian filter is applied to the center of an image {e.g., the center 410 in FIG.4A). flipped to favor features around the middle. These preferred features are used for autoencoding, followed by a density-based spatial cluster of applications using a noise (DBSCAN}-based clustering algorithm.,
    In some embodiments, the quality of a classification or cluster of features is further characterized by determining a distance metric for each feature in the classification, the distance metric indicating the feature's deviation from the mean cluster image Distance metric measured using the cosine distance of the features within the classification. In FIG. 5, features in the classification are sorted by the calculated distance metric, and features with the greatest distance have a higher priority for discrimination. This helps identify minor discrepancies by giving priority to potentially different characteristics. For example, images 510 and 515 in FIG. 5 compared to the other images in FIG. 5 foreign features along the upper right edge of the image. Higher priority errors may need to be inspected separately. When
    it is found that features with higher priority have a different error
    11 represent, they can be fed back into the process to improve future classification.
    FIG. 6 illustrates an example of a computing hardware device 600 that may be used to perform the calculations described in this disclosure. The computer hardware device 600 includes a central processing unit (CPU) 602 with attached main memory 604. The CPU may include, for example, eight processing cores, thereby improving the performance of all multi-threaded portions of the computer software. For example, the size of main memory 604 may be 64 G bytes. The CPU 602 is connected to a Peripheral Component Interconnect Express (PCle) bus 620 . A graphics processing unit (GPU) 614 is also connected to the PCIe bus. In the computing hardware device 600, the GPU 614 may or may not be connected to a graphics output device such as a video monitor. When not connected to a graphics output device, the GPU 614 can be used as a pure, high-speed, parallel computing unit. The computer software can achieve significantly higher performance by using the GPU for part of the calculations compared to using the CPU 602 for all calculations. The CPU 602 communicates with the GPU 614 via the PCIe bus 620. In other embodiments (not shown), the GPU 614 may be integrated into the CPU 602 instead of being connected to the PCIe bus 620. The hard drive controller 608 can also be connected to the PCIe bus by connecting two hard drives 610 to the hard drive controller 608, for example. Finally, a local area network (LAN) controller 612 may also be attached to the PCIe bus and provide Gigabit Ethernet (GbE) connectivity to other computers. In some embodiments, computer software and/or design data is stored on hard drives 610 . In other embodiments, either the computer programs or the design data, or both the computer programs and the design data, can be accessed from other computers or file server hardware over the GbE Ethernet
    be accessed.
    FIG. 7 is a flow chart 700 illustrating methods for matching features in electronic designs, such as patterns for solid state or flat panel displays. For example, flow 700 may use an autoencoder that has already been trained with patterns for solid state or flat panel displays. Process 700 begins with step 702 of entering a set of pattern data, where the set of pattern data may be patterns for solid state or flat panel displays. The set of pattern data includes a variety of features. In some embodiments, the set of pattern data is SEM images or simulated SEM images, and the set of pattern data may include a suspect site set from the mask inspection. Step 704 involves using a trained neural network on the set of template data to classify the set of template data. Each feature of the plurality of features is classified, the classifying being based on a geometric context defined by shapes in a region and the classifying using machine learning techniques. In some embodiments of FIG. 7, the set of pattern data includes a set of reported errors from a geometric examiner. In some embodiments, the methods include determining (i.e., calculating) a distance metric in step 708 for each feature in a classification created by the classifying of step 704. The distance metric can be measured, for example, using a cosine distance of the features within the classification. Step 710 involves sorting the pattern data into each classification. In step 712, based on the sorting of the pattern data in each classification, a determination is made of a set of patterns for further inspection.
    FIG. 8 is a flowchart 800 depicting methods for determining optimal OPC patterns for electronic designs, such as a semiconductor pattern or a flat panel display. For example, flow 800 may use an autoencoder that has already been trained with patterns for solid state or flat panel displays. Flow 800 begins with step 802, entering a set of sample data, the set of
    Pattern data includes a variety of features. At the set of
    13 Pattern data may be simulated mask data enhanced by OPC (i.e., OPC patterns for a mask design). Step 804 involves using a trained neural network on the set of template data to classify the set of template data. Each feature of the plurality of features is classified, the classifying being based on a geometric context defined by shapes in a region and the classifying using machine learning techniques. In some embodiments of FIG. 8, the methods include the step 806 of determining (i.e. generating) a mean image for each classification produced by the classification and a variation between the features in the classification. In step 808, a determination of matching patterns can be made using the classifications, where the matching features can be used to determine, for example, an optimal OPC method for a mask design (e.g., determining groupings with less or the least deviation, as indicated by the blur relative to FIGS.4A-4F).
    In embodiments of FIG. 7 and 8, the methods include compressing, for example using an autoencoder, the input set of pattern data into compressed pattern data, and classifying (e.g., steps 704 or 804) using the compressed pattern data. The compression produces encoded features, where each encoded feature produced by the autoencoder can be an element in a vector. In embodiments of FIG. 7 and 8, an autoencoder is used for classification. The classification may allow a feature in the plurality of features to be included in more than one classification. In embodiments of FIG. 7 and 8, the methods further include applying a Gaussian filter to the center of an image to prefer features around the center.
    Although the specification has been detailed with respect to specific embodiments, it should be understood that those skilled in the art, once understanding the foregoing, can readily contemplate modifications, variations, and equivalents to these embodiments. this and
    other modifications and variations of the present methods may be devised
    14 can be carried out by persons of ordinary skill in the art without departing from the scope of the present subject matter, which is particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will recognize that the foregoing description is exemplary only and is not intended to be limiting. The steps set forth in this specification may be added to, removed from, or modified without departing from the scope of the invention. In general, all flowcharts presented are intended to show only one possible sequence of basic operations to achieve a function, with many variations being possible. Thus, it is intended that the present subject matter cover such modifications and variations as may come within the scope of
    appended claims and their equivalents.
    权利要求:
    Claims (1)
    [1]
    Patent Claims:
    1. A method of matching features in electronic design patterns, the method comprising:
    inputting a set of pattern data for solid state or flat panel displays, the set of pattern data including a plurality of features; and
    classifying each feature in the plurality of features, wherein the classifying is based on a geometric context defined by shapes in a region, and wherein the classifying uses machine techniques
    learning.
    2. The method of claim 1, further comprising compressing the input set of pattern data into compressed pattern data, where
    the compressed sample data are used in classifying.
    3. The method of claim 2, wherein in the compressing
    autoencoder is used.
    4. The method of claim 3, wherein each of the autoencoder
    generated encoded feature is an element in a vector.
    5. The method of claim 1, wherein the classifying a
    autoencoder is used.
    6. The method of claim 1, wherein the classifying allows a feature in the plurality of features to be included in more than one classification
    is included.
    7. The method of claim 1, wherein the set of pattern data is a
    Set of questionable spots from mask inspection included.
    proximity correction - OPC) have been improved.
    9. The method of claim 1, further comprising determining an average image for each classification produced by the classifying and a
    Variation among the variety of characteristics included in the classification.
    10. The method of claim 1, wherein the set of pattern data is a
    Set of errors reported by a geometric examiner.
    11. The method of claim 10, further comprising determining a distance metric for each feature in the plurality of features in a by
    Classify created classification includes.
    12. The method of claim 11, wherein the distance metric using a cosine distance of the features in the plurality of features
    is measured within the classification.
    13. The method of claim 1, further comprising applying a Gaussian filter to a center of an image to attract features around the center
    prefer
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    申请号 | 申请日 | 专利标题
    US201962810168P| true| 2019-02-25|2019-02-25|
    US16/793,390|US11263496B2|2019-02-25|2020-02-18|Methods and systems to classify features in electronic designs|
    PCT/IB2020/051496|WO2020174342A1|2019-02-25|2020-02-22|Methods and systems to classify features in electronic designs|
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